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Santa Clara, CA, 2009-08-31 19:11:59
JEDEC Solid State Technology Association and MindShare have teamed up to offer exceptional technical education classes related to JEDEC standards including new information on the JEDEC DDR3 specification and its latest updates.
DRAMs used in computers have ranged from asynchronous DRAMs through today's DDR3 SDRAMs. MindShare’s DRAM Technology Architecture course describes the development of computer memory systems and covers in-depth today’s most advanced DRAM technology. The course ultimately focuses on ultra-dense, high-speed DDR2/DDR3 technology. Memory cell theory, operation and key chip architecture differences from SDRAM through DDR3 are covered. The DIMM organization and raw card definitions will be covered, as well as bus implementations. Initialization of a memory module, including an overview of the SMBus protocol and how to use the address strapping is discussed.
System design challenges, ranging from signal routing to error handling, are covered. Using waveform examples, the commands and basic differences between SDRAM, DDR, DDR2 and DDR3 are taught. DRAM controller design principles are also discussed. JEDEC announced the release of JESD 79-3C, which defines the JEDEC DDR3 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. Learn how these enhancements for JEDEC DDR3 will enable improved system performance, including increased memory densities in server applications and reduction in costs for thermal management.
The class is taught by John Swindle over two days, from 9/10-9/11/2009 in Santa Clara, CA. The course runs from 8:30 am to 5:00 pm each day. Lunch is included.
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